The present invention relates to a bus access controller, and more particularly, to a bus access controller which changes bus width for data transfer.
In a conventional PCI device supporting a 64-bit bus, if the high 32-bit bus fails, the system ends abnormally after reporting the fault as a critical error even if the low 32-bit bus has no problem.
Japanese Patent Application Laid-Open Hei No. 5-257871 discloses a data bus control system which continues data transfer between a control circuit and a disk drive using a first bus if a second bus fails while transferring data through the first and second buses.
The above data bus control system has an error detection circuit provided on the first and second buses, and uses the second bus when the error detection circuit detects that the first bus fails. However, bus width for data transfer is selected after a request source starts the data transfer. This creates a problem because the system cannot correct an error on the bus between the request source and the control circuit.
An object of the invention is to provide a bus access controller which performs a data transfer from a request source by using a low order bus if a high order bus fails and the low order bus is operating normally.
Another object of the invention is to provide a bus access controller which transfers data after selecting a transfer mode at the time of requesting data transfer.
Another object of the invention is to provide a bus access controller which can handle intermittent faults and faults of the low order bus.
According to one aspect of the present invention, a bus control circuit is provided which includes: a first element which detects a fault of one part of the bus when data is sent through all part of the bus; and a second element which output a signal showing that it is impossible to send data through all parts of the bus to the request source when the first element detects the fault.
According to another aspect of the present invention, a bus control circuit is provided which includes: a first element which observes a signal on a low order of the bus; a second element which detects a fault of the first element; a third element which selects and outputs the signal on the low order of the bus or a signal on a high order of the bus based on the detection performed by the second element; and a fourth element which observes an output from the third element.
According to another aspect of the present invention, a bus control system is provided which includes: a host device; a control circuit; a bus which connects the host device and the control circuit and includes a first part and a second part; a first element which is provided in the control circuit and detects a fault in the first part when the host device sends data through the first and second parts; a second element which is provided in the control circuit and outputs a signal indicating that it is impossible to send data through the first and second parts to the host device; and third element which is provided in the host device, receives the signal and starts to send data through the second part.